Typically, the code conversion of the type stated above is carried out by means of two decoders. When a binary code representing the value i is applied, a first decoder develops a signal "1" only on the (i+1)-th one of a plurality of output lines thereof, and develops a signal "0" on all of the remaining output lines. The second of the two decoders receives outputs of the first decoder and develops the signal "1" on all of the first to the i-th ones of a plurality of output lines thereof and the signal "0" on all of the remaining output lines. Alternatively, the second decoder receives output signals from the first decoder and develops the signal "1" on all of the i most significant output lines and the signal "0" on all of the remaining output lines.
An example of a circuit which may be used as the second decoder is disclosed in of Japanese Unexamined Patent Publication No. SHO 63-156427. The circuit of this publication is called an decoding circuit" and includes a number of gates serially connected between a voltage supply and a point of reference potential. Respective outputs from a first decoder are coupled to corresponding gates of the second decoder. Output lines are derived from respective junctions between adjacent ones of the gates.
The second decoder of the above-described type requires a large number of transmission gates for handling a large value. For example, for a value i in a range of from 0 to 30, thirty (30) transmission gates must be connected in series, causing an increase in capacitance provided by diffusion layers of transistors constituting the gates as well as an increase in capacitance and resistance associated with wiring for the transistors. This could cause instability in circuit performance or reduce operating speed.
Another type of conventional circuit which may be used as the second decoder includes a number of OR gates connected in series, as shown in prior art FIG. 3. Respective first decoder outputs are coupled to the respective ones of the OR gates. The output of the second decoder is derived from the respective OR gates. In this type of decoder, when an input signal "1" is applied to a more significant OR gate, the signal must cause less significant OR gates successively to be enabled, which results in significant delay in operation.
Accordingly, a major object of the present invention is to provide a second decoder which can operate stably and at a high speed.